In high-precision analog (or mixed signal) applications, a low flicker noise (i.e., 1/f noise) for metal-oxide-semiconductor field-effect transistors (MOSFETs) is one of the important design requirements. Generally, flicker noise is attributed to the trapping and de-trapping of carriers by traps at the Si—SiO2 surface.
Traditionally in older generations of complementary-metal-oxide-semiconductor (CMOS) technology prior to 0.25 um CMOS, input devices of an operation amplifier (op-amp) uses a p-channel MOSFET (PMOS), which is a buried channel device. For these type of op-amps, flicker noise is low for PMOS devices as compared to n-channel MOSFETs (NMOS, which are surface channel devices) because flicker noise is reduced by making MOSFET conduction away from the surface by having a buried channel device. When the conduction is not at the surface, the carriers in the buried channel PMOS (BCPMOS) are less impacted by trapping and de-trapping.
As CMOS technology moved through several generations of scaling below 0.25 um nodes, the BCPMOS became replaced by a surface channel PMOS (SCPMOS) as the industry move to accommodate digital applications where the issue of flicker noise is not a primary concern. However, for high precision analog (or mixed signal) applications, the high flicker noise caused by SCPMOS devices remains problematic.